Clock Generators

Divide-by-3 Clock (50% Duty)

A divide-by-3 clock generator that produces a 50% duty cycle output using a 2-bit state machine.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Divide-by-3 Clock (50% Duty) is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This module provides a robust, synchronous divide-by-3 clock generator with a guaranteed 50% duty cycle.

It is designed for systems requiring odd-frequency dividers without duty cycle distortion.

The design uses a simple 2-bit state machine with asynchronous reset and XOR-based output generation.

Choose Open in IDE. RTL Studio loads the packaged workspace for Divide-by-3 Clock (50% Duty).
Read the Verilog module in the editor. The catalog line for this block: A divide-by-3 clock generator that produces a 50% duty cycle output using a 2-bit state machine.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Division Ratio: Divides input clock frequency by 3.
Duty Cycle: Maintains a strict 50% duty cycle on the output clock.
Reset: Asynchronous active-low reset (rst_n_i).
State Machine: Uses a 2-bit Gray-code-like sequence (00 -> 01 -> 10 -> 00).
Verification: Verified with Icarus Verilog simulation including reset, frequency, and duty cycle checks.

Ports

Port Name	Direction	Width	Description
`clk_i`	Input	1	Clock input
`rst_n_i`	Input	1	Active-low asynchronous reset
`clk_o`	Output	1	Divided clock output (50% duty cycle)

Architecture

The module uses a 2-bit register to track the state. The state transitions follow the sequence 00 -> 01 -> 10 -> 00. This sequence ensures that only one bit changes at a time during transitions, minimizing glitches.

The output clock is generated by XORing the two state bits (state_r[0] ^ state_r[1]). This XOR operation produces a 50% duty cycle for the mod-3 counter sequence.

Verification

The testbench performs three key checks:

TC1: Verifies the reset state is zero.
TC2: Counts transitions to ensure the frequency is correct.
TC3: Measures high and low times to verify the duty cycle.

Expected Output:

TC1 Reset check PASS
TC2 Frequency check PASS, transitions=6
TC3 Duty cycle check PASS, high=5, low=4
INFO: PASS

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