Clock Generators

Clock Enable with Soft-Reset Stretch — L2 Upgrade

Configurable clock enable generator with stretch and phase offset capabilities for precise timing control.

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Clock Enable with Soft-Reset Stretch — L2 Upgrade is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a configurable clock enable generator with stretch and phase offset capabilities. It allows precise control over CE signal timing relative to input pulses. The module supports independent stretch and phase offset configurations. Stretch logic extends the CE pulse duration based on a counter. Phase offset logic delays the CE pulse start based on a counter. The output is the logical OR of stretch and phase flags. This design is suitable for power management and synchronized data path control.

This IP provides a robust solution for clock enable timing control. It supports stretch and phase offset configurations. The design is verified and ready for integration. Use this module to manage power and synchronization in digital designs.

Choose Open in IDE. RTL Studio loads the packaged workspace for Clock Enable with Soft-Reset Stretch — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Configurable clock enable generator with stretch and phase offset capabilities for precise timing control.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Supports configurable stretch count via stretch_cnt input. Supports configurable phase offset via phase_offset input. Asynchronous active-low reset rst_n clears all internal state. Synchronous operation on positive clock edge clk. 4-bit width for both stretch and phase counters. Simple interface with single bit inputs and outputs.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low asynchronous reset
ce_in	Input	1	Input clock enable pulse
stretch_en	Input	1	Enable stretch logic
stretch_cnt	Input	[3:0]	Stretch counter value
phase_offset	Input	[3:0]	Phase offset counter value
ce_out	Output	1	Generated clock enable output

Verification

The testbench verifies four key scenarios. Reset behavior ensures output is low during reset. Stretch test verifies pulse extension duration. Phase offset test verifies pulse delay duration. Combined test verifies interaction of both features. All tests passed in simulation.

Test Case	Description	Result
TC1	Reset Test	PASS
TC2	Stretch Test	PASS
TC3	Phase Offset Test	PASS
TC4	Combined Test	PASS

More in Clock Generators

All Clock Generators blocks