Clock Generators

CE Pulse Every N Cycles

Generates a single-cycle clock enable pulse every N clock cycles when enabled.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

CE Pulse Every N Cycles is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

A synthesizable Verilog module that generates a single-cycle Clock Enable (CE) pulse every N clock cycles. This IP is designed to drive lower-frequency logic from a high-speed clock domain, ensuring precise timing control.

This IP provides a simple and reliable way to generate periodic clock enable pulses.

It is suitable for low-frequency peripheral interfacing and clock division tasks.

Choose Open in IDE. RTL Studio loads the packaged workspace for CE Pulse Every N Cycles.
Read the Verilog module in the editor. The catalog line for this block: Generates a single-cycle clock enable pulse every N clock cycles when enabled.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Configurable Period: Set the pulse frequency via a 32-bit input parameter n.
Synchronous Control: Supports synchronous reset (rst_n) and enable (en) signals.
Safe Operation: Handles n=0 by defaulting to a period of 1 cycle to prevent undefined behavior.
Verified: Tested with Icarus Verilog simulation.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`en`	Input	1	Enable signal; pulse generation is active only when high
`n`	Input	32	Period divisor; determines pulse frequency
`ce_pulse`	Output	1	Single-cycle pulse asserted every N clocks

Architecture

The design utilizes a 32-bit counter that increments on every clock cycle while the en signal is high.

Counting: The counter resets to zero when it reaches n - 1 (or n_safe - 1 if n was clamped).
Enable Handling: If en is low, the counter immediately resets to zero. This ensures that the pulse generation does not persist across enable gaps.
Pulse Generation: The ce_pulse output is asserted for exactly one clock cycle when the counter equals n_safe - 1.

Verification

The testbench verifies the following scenarios using Icarus Verilog:

Test Case	Description	Result
TC1	N=2, en=1	PASS
TC2	N=3, en=1	PASS
TC3	N=5, en=1	PASS
TC4	en=0 (Pause)	PASS

### Running Simulations

Ensure Icarus Verilog is installed.
Run the simulation script provided in the repository.
Inspect sim/dump.vcd using a waveform viewer (e.g., GTKWave or RtlStudio) for detailed timing analysis.

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