Clock Generators

1-Cycle Data Delay

A registered delay element that holds input data for one clock cycle with asynchronous reset and synchronous enable.

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About this block

Simulate it in the Verilog IDE

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1-Cycle Data Delay is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

A simple 1-cycle registered delay element with asynchronous reset and synchronous enable. This IP is designed for pipeline synchronization and simple buffering tasks in digital designs.

This IP provides an 8-bit wide data path that delays input data by exactly one clock cycle. It supports asynchronous active-low reset and synchronous enable control, making it suitable for basic data alignment and buffering in synchronous digital systems.

Choose Open in IDE. RTL Studio loads the packaged workspace for 1-Cycle Data Delay.
Read the Verilog module in the editor. The catalog line for this block: A registered delay element that holds input data for one clock cycle with asynchronous reset and synchronous enable.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

One-cycle registered delay: Output reflects input data from the previous clock cycle.
Asynchronous Active-Low Reset: rst_n forces output to zero immediately, independent of the clock.
Synchronous Enable: en allows conditional data capture on the rising clock edge.
8-bit Data Width: Configurable general-purpose data path (din/dout).

Ports

Port	Direction	Width	Description
clk	Input	1	Clock signal
rst_n	Input	1	Asynchronous active-low reset
en	Input	1	Synchronous enable
din	Input	8	Data input
dout	Output	8	Delayed data output

Verification

The provided testbench (tb_cycle_delay_1.v) validates the following scenarios:

Test Case	Description	Expected Result
TC1	Reset value is 0	`dout` becomes 0 after reset deassertion
TC2	Single cycle delay with enable	`dout` reflects `din` after 1 cycle
TC3	Hold when disable	`dout` retains value when `en` is low
TC4	New value with enable	`dout` updates to new `din` when `en` is high

### Simulation Log

Upon running the simulation, the log should display:

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