Clock Generators

Clock-Enable Divider (CE Pulse) — L1 Upgrade — L2 Upgrade

Glitch-free clock enable divider with M/N inputs. Generates a pulse on ce_out when counter reaches M-1. Counter resets when reaching N-1. M must be <= N.

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About this block

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Clock-Enable Divider (CE Pulse) — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

A glitch-free, configurable clock-enable pulse generator. This IP generates a single-cycle enable pulse (ce_out) based on two configurable parameters, M and N, synchronized to the input clock clk.

This IP provides a robust, glitch-free clock-enable divider with dynamic M/N control.

It is suitable for power gating or clock gating applications requiring precise pulse timing.

Choose Open in IDE. RTL Studio loads the packaged workspace for Clock-Enable Divider (CE Pulse) — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Glitch-free clock enable divider with M/N inputs. Generates a pulse on ce_out when counter reaches M-1. Counter resets when reaching N-1. M must be <= N.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Glitch-Free Output: The output ce_out is derived from registered counter values, ensuring no glitches occur during state transitions.
Configurable Division: Supports dynamic configuration of the division ratio via m (pulse position) and n (modulus) inputs.
Synchronous Enable: The counter only increments when the input enable ce_in is high.
Asynchronous Reset: Supports active-low asynchronous reset for immediate initialization.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`m`	Input	8	Pulse position index (0 to N-1)
`n`	Input	8	Counter modulus (1 to 255)
`ce_in`	Input	1	Input clock enable
`ce_out`	Output	1	Glitch-free clock enable pulse

Architecture

The design uses a single 8-bit counter registered on the positive clock edge. Comparison logic detects when the counter equals m - 1 or n - 1. The ce_out signal is assigned directly from the compare_m wire. Since compare_m is derived from the registered cnt, it is free of combinational glitches relative to the clock domain.

Verification

The testbench verifies reset behavior, pulse generation at various M values, and counter reset at N. It also checks that the counter holds its value when ce_in is de-asserted.

### Test Cases

Test Case	Description	Result
TC1	Reset check	PASS
TC2	Pulse at M=3	PASS
TC3	Reset at N=8	PASS
TC4	Disable check	PASS
TC5	Pulse at M=3 with N=10	PASS
TC6	Pulse at M=4 with N=8	PASS

### Simulation Results

After running the simulation, the Log panel should show:

TC1 PASS reset check
TC2 PASS pulse at M=3
TC3 PASS reset at N=8
TC4 disable check
TC5 PASS pulse at M=3
TC6 PASS pulse at M=4
Simulation ends with INFO: PASS.

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