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Clock Generators

Lost-Clock Detector — L2 Upgrade

Dual-phase lost-clock detector with configurable threshold and count enable.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Lost-Clock Detector — L2 Upgrade is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a robust, dual-phase lost-clock detector for Verilog designs. It monitors a target clock (clk_mon) against a reference clock domain (clk_ref) and asserts an alarm signal when the monitored clock stops toggling.

The design ensures glitch-free edge detection through dual-phase synchronization and provides configurable latency thresholds. It is synthesis-ready, verified with Icarus Verilog, and includes features such as synchronous count enable and active-low reset for deterministic behavior.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Lost-Clock Detector — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Dual-phase lost-clock detector with configurable threshold and count enable.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Dual-Phase Synchronization: Ensures glitch-free edge detection and prevents metastability issues when crossing from clk_mon to clk_ref.
  • Configurable Threshold: Supports various latency requirements via an 8-bit threshold counter (default 8-bit width, extensible).
  • Count Enable (CE): Allows dynamic pausing of the monitoring process without resetting the state.
  • Active-Low Reset: Ensures deterministic startup behavior by clearing the counter and alarm state immediately.
  • Glitch-Free Output: Registered alarm output prevents metastability propagation to downstream logic.

Ports

PortDirectionWidthDescription
clk_refInput1Reference clock (always running, synchronous domain)
clk_monInput1Monitored clock (may stop, glitch, or be asynchronous)
rst_nInput1Active-low reset (synchronous to clk_ref)
threshInput[7:0]Threshold count (cycles of clk_ref) before alarm
ceInput1Count enable (synchronous to clk_ref; 1=enable, 0=freeze)
alarmOutput1Asserted high when clk_mon is lost for > thresh cycles

Verification

The provided testbench (tb_lost_clock_detector_dual_phase.v) validates five key scenarios:

  1. Normal Operation: Confirms no false alarms during active clock.
  2. Lost Clock Detection: Verifies alarm assertion after threshold cycles of inactivity.
  3. Reset Behavior: Ensures immediate clearing of alarm and counter on reset.
  4. Count Enable Freeze: Confirms detection pauses when CE=0.
  5. Custom Threshold: Validates configurable latency settings.

### Running Simulation

  1. Ensure Icarus Verilog is installed.
  2. Run the simulation script:
  3. Check the Log panel for the following expected results:

- TC1 PASS - Alarm low as expected - TC2 PASS - Alarm asserted after clock loss - TC3 PASS - Alarm cleared on reset - TC4 PASS - Alarm not asserted when CE=0 - TC5 PASS - Alarm asserted with custom threshold - INFO: PASS

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