Clock Generators
2:1 Clock Divider (Toggle Flip-Flop)
A simple toggle flip-flop that divides the input clock frequency by two.
About this block
Simulate it in the Verilog IDE
2:1 Clock Divider (Toggle Flip-Flop) is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This OpenIP provides a minimal, resource-efficient 2:1 clock divider implemented using a single toggle flip-flop. It halves the input clock frequency and includes an asynchronous active-low reset. The design is verified for basic toggle and reset functionality, making it suitable for simple clock domain crossing or frequency division needs in low-frequency applications.
This OpenIP implements a simple 2:1 clock divider using a toggle flip-flop. The output clock frequency is exactly half of the input clock frequency. The design is suitable for low-frequency clock generation or simple timing references.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 2:1 Clock Divider (Toggle Flip-Flop).
- Read the Verilog module in the editor. The catalog line for this block: A simple toggle flip-flop that divides the input clock frequency by two.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Architecture
The core logic consists of a single D-type flip-flop with inverted feedback. The output toggles state on every rising edge of the input clock. Asynchronous active-low reset forces the output to a known low state. The implementation is fully synchronous except for the reset mechanism.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| clk | Input | 1 | Main clock input |
| rst_n | Input | 1 | Active-low asynchronous reset |
| clk_out | Output | 1 | Divided clock output (freq/2) |
Verification
The testbench validates reset behavior and toggle functionality. Five specific test cases ensure correct operation across multiple cycles. All tests passed successfully in the Icarus Verilog simulation environment.
| Test Case | Description | Result |
|---|---|---|
| TC1 | Verify reset state is 0 | PASS |
| TC2 | Verify first toggle to 1 | PASS |
| TC3 | Verify second toggle to 0 | PASS |
| TC4 | Verify third toggle to 1 | PASS |
| TC5 | Verify frequency halving stability | PASS |
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