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Clock Generators

Glitch-Free Clock Select 2 — L2 Upgrade

Glitch-free clock selector with busy indicator for two asynchronous clock sources.

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About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

Glitch-Free Clock Select 2 — L2 Upgrade is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP provides a simple, glitch-free clock selector for two asynchronous input clocks (clk_a and clk_b). It ensures safe switching between clock sources by gating the inputs with enable signals derived from a selection control (sel). A busy output signal indicates when the clock output is stable and valid, which is high after reset deassertion.

This module is classified as Level 2 difficulty, suitable for educational purposes and basic clock domain management.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Glitch-Free Clock Select 2 — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Glitch-free clock selector with busy indicator for two asynchronous clock sources.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Glitch-Free Switching: Uses enable logic to prevent output glitches during clock source transitions.
  • Asynchronous Support: Handles clock sources with different frequencies and phases.
  • Busy Indicator: Provides a busy signal that goes high after reset, indicating the output clock is valid.
  • Simple Interface: Minimal port count for easy integration.

Ports

PortDirectionWidthDescription
clk_aInput1Primary clock input
clk_bInput1Secondary clock input
selInput1Selection control (1 = clk_a, 0 = clk_b)
rst_nInput1Active-low synchronous reset
clk_outOutput1Selected glitch-free clock output
busyOutput1High when clock output is valid (high after reset)

Architecture

The module implements a glitch-free mux using enable gating. Two enable registers (en_a and en_b) are driven by their respective clock domains. The sel signal controls these enables:

  • If sel is high, en_a is asserted, allowing clk_a to pass through an AND gate.
  • If sel is low, en_b is asserted, allowing clk_b to pass through an AND gate.
  • The outputs of these AND gates are ORed together to produce clk_out.

This structure ensures that only one clock path is active at any time, preventing glitches. The busy signal is set high immediately after the reset rst_n is deasserted, indicating that the clock output is stable.

Verification

The provided testbench verifies the following behaviors:

  • Reset behavior: busy goes high after reset deassertion.
  • Clock selection: clk_out follows the selected clock source.
  • Transition stability: busy remains high during switches.

### Expected Simulation Results

After running the simulation, the log should display:

  • TC1 PASS: busy high after reset
  • TC2 PASS: clk_out follows clk_a
  • TC3 PASS: clk_out follows clk_b
  • TC4 PASS: busy high during A->B switch
  • TC5 PASS: busy high during B->A switch
  • INFO: PASS

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