Clock Generators

Fractional Clock Divider with Jitter Control

Synthesizable fractional clock divider using phase accumulation for low jitter.

Open in IDE Category Wiki · clock

About this block

Simulate it in the Verilog IDE

Mediumsystemverilogsimsyn

Fractional Clock Divider with Jitter Control is a SystemVerilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This OpenIP provides a synthesizable fractional clock divider that uses scaled counter and duty-cycle parameters to generate an output clock from a faster input.

The output frequency follows F_out = F_in / (N + F/D), where N is the integer divisor, F is the fractional numerator, and D is the fractional denominator.

Duty cycle is controlled with DUTY_NUM and DUTY_DEN so integrators can target non-50% high-time ratios when needed.

Choose Open in IDE. RTL Studio loads the packaged workspace for Fractional Clock Divider with Jitter Control.
Read the SystemVerilog module in the editor. The catalog line for this block: Synthesizable fractional clock divider using phase accumulation for low jitter.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port	Direction	Width	Description
`clk_i`	input	1	Input clock source
`rst_n_i`	input	1	Active-low asynchronous reset
`clk_o`	output	1	Divided clock output

Parameters

Parameter	Default	Description
`WIDTH`	16	Internal counter width
`N`	2	Integer divisor part
`F`	1	Fractional numerator (0 <= F < D)
`D`	2	Fractional denominator
`DUTY_NUM`	1	Duty-cycle numerator
`DUTY_DEN`	2	Duty-cycle denominator

Architecture

The divider computes TOTAL_PERIOD = N*D + F and scales it by DUTY_DEN to keep integer compare thresholds. A free-running counter toggles clk_o at the high-period boundary and at the end of each full period.

Verification

Test Case	Description	Expected Behavior
TC1	Default fractional ratio	Output period matches N=2, F=1, D=2 configuration
TC2	Fractional division check	2.5x division behavior verified
TC3	Edge case D=1	Integer-only division path handled
TC4	Edge case F=0	Pure integer divisor N handled
TC5	Duty cycle	Configured duty ratio honored

Run simulation with make sim from the variant directory.

Integration

Ensure WIDTH is large enough for FULL_PERIOD = (N*D + F) * DUTY_DEN. Synchronize or qualify downstream logic that samples clk_o because the output is registered on clk_i. Apply timing constraints on the counter compare path when the input clock is high frequency.

More in Clock Generators

All Clock Generators blocks