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Clock Generators

Integer Clock Divider

Parameterized integer clock divider with 50% duty cycle supporting even divisors from 2 to 255.

Open in IDE Category Wiki · clock

About this block

Simulate it in the Verilog IDE

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Integer Clock Divider is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

A parameterized Verilog module implementing an integer clock divider with a strict 50% duty cycle. It supports divide-by-N ratios where N is an even integer between 2 and 255.

This module generates a divided clock signal from a main input clock. It uses a toggle flip-flop architecture driven by a counter to ensure symmetric high and low periods (50% duty cycle). It is designed for even divisors only. The module includes synchronous enable control and active-low asynchronous reset.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Integer Clock Divider.
  2. Read the Verilog module in the editor. The catalog line for this block: Parameterized integer clock divider with 50% duty cycle supporting even divisors from 2 to 255.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Parameterizable: Set division ratio via DIVISOR parameter (2 to 255, even numbers only).
  • 50% Duty Cycle: Guaranteed symmetric output for even divisors.
  • Synchronous Enable: en signal allows clock gating.
  • Asynchronous Reset: rst_n initializes the counter and output.
  • Minimal Area: Simple toggle flip-flop design.

Interface

PortDirectionWidthDescription
clkInput1Main clock input
rst_nInput1Active-low asynchronous reset
enInput1Synchronous enable signal
clk_outOutput1Divided clock output

Architecture

The design counts from 0 to DIVISOR - 1 on each active clock edge. When the counter reaches the maximum value, it resets to zero, and the output toggle flip-flop inverts its state. This results in an output period of DIVISOR * CLK_PERIOD.

Verification

The testbench (tb/tb_clock_divider_int.v) validates:

  1. Different divisors produce different frequencies.
  2. Reset initializes outputs to zero.
  3. Simulation completes without errors.

### Running Tests

More in Clock Generators

All Clock Generators blocks