Clock Generators

Parameterized Clock Enable Generator — L2 Upgrade

A parameterized clock enable generator that produces a periodic enable pulse based on M/N division parameters, with global reset and enable control.

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Parameterized Clock Enable Generator — L2 Upgrade is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a parameterized clock enable generator with M/N frequency division. It generates a periodic enable pulse based on configurable M (pulse width) and N (period) parameters.

The ce output is high for M cycles and low for N-M cycles within an N-cycle period. The used signal mirrors ce to indicate active usage cycles. The module supports global reset and a synchronous enable control.

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RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Configurable Duty Cycle: Defined by the m parameter (pulse width).
Configurable Period: Defined by the n parameter (total period).
Synchronous Reset: Active-low polarity (rst_n).
Global Enable: Synchronous control signal (en) to gate the generator.
32-bit Parameters: Supports large M and N values for low-frequency division.
Registered Outputs: ce and used are registered to ensure stable timing and reduce glitches.
Low Resource Utilization: Optimized for FPGA and ASIC targets.

Ports

Port	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low synchronous reset
m	Input	32	Enable pulse width (cycles)
n	Input	32	Period length (cycles)
en	Input	1	Global enable control
ce	Output	1	Clock enable pulse
used	Output	1	Active usage indicator

Architecture

The design uses a 32-bit counter that resets when it reaches N-1. The counter increments on every clock cycle when en is asserted. The ce signal is asserted when the counter value is less than M. The used signal mirrors the ce logic for explicit usage tracking. Both outputs are registered to ensure stable timing.

### Logic Flow

Counter: Increments on posedge(clk) if en is high. Resets to 0 if rst_n is low or if counter == n - 1.
CE Generation: Asserted if en is high AND counter < m AND m > 0.
Used Generation: Mirrors ce logic.

Verification

The testbench validates reset behavior, basic M/N generation, edge cases, and enable gating. All five test cases pass successfully in Icarus Verilog simulation.

### Expected Results

After Run Simulation, the Log panel should show:

TC1 PASS Reset state correct
TC2 PASS Basic M/N generation correct
TC3 PASS M=0 correct
TC4 PASS M=N correct
TC5 PASS En=0 correct
Simulation ends with INFO: PASS

### Test Cases

Test Case	Description	Result
TC1	Reset state verification	PASS
TC2	Basic M=4, N=8 generation	PASS
TC3	M=0 (No enable)	PASS
TC4	M=N (Always enable)	PASS
TC5	Enable gating (en=0)	PASS

More in Clock Generators

All Clock Generators blocks