Clock Generators

Pulse-to-Toggle Clock Maker — L1 Upgrade — L2 Upgrade

Converts an asynchronous pulse into a glitch-free toggled clock output with configurable duty cycle and enable control.

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About this block

Simulate it in the Verilog IDE

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Pulse-to-Toggle Clock Maker — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core converts an asynchronous input pulse into a glitch-free, toggled clock output. The output frequency and duty cycle are configurable via parameters m (on-time) and n (off-time). The design ensures glitch-free transitions by latching state changes only on clock edges.

This module generates a square wave output (toggle_out) triggered by a single pulse (pulse_in).

The output toggles state upon receiving a pulse and maintains that state for a duration determined by m (high time) and n (low time) relative to the input clock clk.

Choose Open in IDE. RTL Studio loads the packaged workspace for Pulse-to-Toggle Clock Maker — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Converts an asynchronous pulse into a glitch-free toggled clock output with configurable duty cycle and enable control.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Glitch-free Output: State changes are synchronized to the input clock edge, preventing metastability and glitches.
Configurable Duty Cycle: Adjust the on-time (m) and off-time (n) using 8-bit parameters.
Reset Control: Asynchronous active-low reset (rst_n) forces the output to a known low state.
Enable Control: Synchronous enable signal (enable) allows the output to hold its last state when disabled.
Synthesizable: Written in Verilog-2001, compatible with standard synthesis tools.
Verified: Comprehensive testbench included with VCD dump for simulation.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input for synchronization
`rst_n`	Input	1	Asynchronous active-low reset
`pulse_in`	Input	1	Input pulse to trigger toggle
`enable`	Input	1	Synchronous enable signal
`toggle_out`	Output	1	Toggled clock output

Parameters:

m [7:0]: On-duration counter limit (cycles). Default: 8'd10.
n [7:0]: Off-duration counter limit (cycles). Default: 8'd10.

Architecture

The module uses a synchronous counter to manage the toggle period.

Trigger: When pulse_in is detected, the counter resets to 0, and the toggle_reg flips state.
Counting: The counter increments on every posedge(clk) while enable is high.
Period Limit: The total period is defined by m + n. When the counter reaches m + n, it resets to 0.
Output: toggle_out reflects the current state of toggle_reg.

Verification

The testbench verifies five key scenarios:

Test Case	Description	Result
TC1	Initial toggle on pulse	PASS
TC2	State hold when disabled	PASS
TC3	Second toggle after re-enable	PASS
TC4	Toggle with new M/N values	PASS
TC5	Reset functionality	PASS

### Running Simulation

Open your preferred Verilog simulator (e.g., ModelSim, Vivado Simulator).
Compile rtl/pulse_to_toggle_clock_glitch_free_enable_div_used_mn.v and tb/tb_pulse_to_toggle_clock_glitch_free_enable_div_used_mn.v.
Run the simulation.
Check the Log panel for the following output:

More in Clock Generators

All Clock Generators blocks