Clock Generators

Run Window for N Cycles

Generates a busy signal for a configurable number of clock cycles triggered by a start pulse.

Open in IDE Category Wiki · clock

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Run Window for N Cycles is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a run window generator that asserts a busy signal for a configurable number of clock cycles. It accepts a start trigger and a width-8 cycle count input. The busy output remains high until the counter decrements to zero. Subsequent start signals are ignored while the window is active.

This IP provides a reliable mechanism for generating fixed-duration busy windows. It is suitable for controlling peripheral access or state machine timing. The design is fully synchronous and reset-safe. Simulation results confirm correct behavior across all tested conditions.

Choose Open in IDE. RTL Studio loads the packaged workspace for Run Window for N Cycles.
Read the Verilog module in the editor. The catalog line for this block: Generates a busy signal for a configurable number of clock cycles triggered by a start pulse.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Configurable window duration via [7:0] n_cycles input.
Non-retriggerable behavior during active window.
Asynchronous reset deasserts busy and clears the counter.
Synchronous start detection on positive clock edge.
Simple interface suitable for state machine control.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low reset
start	Input	1	Start trigger
n_cycles	Input	8	Number of cycles to run
busy	Output	1	Active-high busy flag

Verification

The testbench verifies four key scenarios:

Reset deasserts the busy signal immediately.
A single start pulse initiates a window of N cycles.
Concurrent start signals during an active window are ignored.
A one-cycle window correctly asserts and deasserts busy.

All test cases passed in simulation.

Test Case	Description	Result
TC1	Reset state verification	PASS
TC2	3-cycle window execution	PASS
TC3	Ignore start while busy	PASS
TC4	1-cycle window execution	PASS

More in Clock Generators

All Clock Generators blocks