Clock Generators
Startup Ready After N Cycles
Asserts a ready signal after a configurable number of clock cycles following reset.
About this block
Simulate it in the Verilog IDE
Startup Ready After N Cycles is a Verilog reference block in the Clock Generators catalog. Clock dividers, gating, and clock distribution helpers. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This IP asserts a ready signal after a configurable number of clock cycles following reset. It supports dynamic configuration of the wait count via the n_cycles and n_cycles_valid inputs. The ready signal is sticky once asserted and remains high until the next reset or valid configuration update.
This IP provides a simple and configurable startup delay mechanism. It is suitable for systems requiring a stable ready signal after power-on or reset.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Startup Ready After N Cycles.
- Read the Verilog module in the editor. The catalog line for this block: Asserts a ready signal after a configurable number of clock cycles following reset.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- Configurable startup delay from 0 to 255 cycles.
- Synchronous reset with active-low polarity.
- Sticky ready output for stable system handshaking.
- Dynamic reconfiguration support via
n_cycles_valid.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| clk | Input | 1 | Clock input |
| rst_n | Input | 1 | Active-low reset input |
| n_cycles | Input | 8 | Number of cycles to wait |
| n_cycles_valid | Input | 1 | Valid signal for n_cycles configuration |
| ready | Output | 1 | Ready signal asserted after N cycles |
Architecture
The module uses a synchronous counter to track the remaining cycles. When n_cycles_valid is asserted, the counter loads the value from n_cycles. The counter decrements on each clock cycle while counting is active. Once the counter reaches zero, the ready signal is asserted and counting stops. The ready signal remains high until a reset occurs or a new valid configuration is provided.
Verification
The testbench verifies the following scenarios:
| Test Case | Description | Expected Result |
|---|---|---|
| TC1 | Reset state | ready is 0 |
| TC2 | N=2 cycles | ready asserts after 2 cycles |
| TC3 | Sticky high | ready remains 1 after assertion |
| TC4 | N=3 cycles | ready asserts after 3 cycles |
All test cases passed successfully.
More in Clock Generators
- 1-Cycle Data Delay
- 16-Bit DDS Phase Accumulator — L2 Upgrade
- 2:1 Clock Divider (Toggle Flip-Flop)
- 4-Phase Clock-Enable Sequencer — L1 Upgrade — L2 Upgrade
- Burst Enable for N Cycles — L1 Upgrade — L2 Upgrade
- CE Pulse Every N Cycles
- Clock Enable with Soft-Reset Stretch — L2 Upgrade
- Clock-Enable Divider (CE Pulse) — L1 Upgrade — L2 Upgrade
- Clock-Enable Stretcher N — L1 Upgrade — L2 Upgrade
- Divide-by-3 Clock (50% Duty)
- Dual-Edge DDR Sampler — L2 Upgrade
- Duty-Correct Divide-by-2 — L1 Upgrade — L2 Upgrade
- Fractional Clock Divider with Jitter Control
- Fractional Clock Enable M/N — L2 Upgrade
- Glitch-Free Clock Select 2 — L2 Upgrade
- Integer Clock Divider