Core-track pattern cards for Learn · RISC-V Core. System / SoC interconnect stays on those Learn pages until the Core notes settle.
Wiki RISC-V
RISC-V
RV32I fields, a fetch/decode/execute sketch, and CSR/trap overview.
Topics
-
RV32I fields
ready
opcode, rd/rs, funct3/7, and the I/S/B/U/J immediates.
-
Fetch, decode, execute
ready
PC+4 fetch, field decode, and a single-cycle or pipelined execute.
-
CSR and traps
ready
Privilege-adjacent control/status and the trap entry/exit sketch.