Wiki SystemVerilog

SystemVerilog

Design-subset SV — types, always_comb/ff, interfaces, and packages.

This section is the synthesizable SV design subset. OOP, constrained-random, and UVM live on the UVM cards and the Learn SV / UVM tracks.

Topics in this section

typedef, enum, and struct ready
Named types for FSM states and packed protocol fields.
Packed vs unpacked ready
How array layout changes slicing, width, and RAM inference.
always_comb and always_ff ready
Explicit combo vs flop processes that lint can check.
Interfaces and modports ready
Bundle a bus once; modports name master vs slave directions.
Packages ready
Shared types and constants with import, without textual macros.