RTL Studio
Open IDE
Wiki Verilog language
wire/reg, buses, assignments, modules, tasks, and headers — the language layer under the RTL blocks.
These pages are the language notes that sit under the theory sections. Hardware patterns (counters, FSMs, RAM) stay in Sequential / FSM; come here for wire vs reg, NBA, and generate companions.
What you can drive with assign vs always, and why SV logic replaces both.
Multi-bit vectors, sized literals, and concatenation.
Why combo uses = and clocked state uses <= .
Instantiation, named port maps, and hierarchy.
Combinational functions vs timed tasks, and $readmem / $display.
include, define, and why localparam usually beats a global macro.