Wiki RISC-V CSR and traps

CSR and traps

Privilege-adjacent control/status and the trap entry/exit sketch.

CSRs are addressed control/status registers (mcause, mepc, mtvec, …). A trap saves PC, jumps to mtvec, and later mrets.

stateDiagram-v2
  [*] --> Run
  Run --> Trap: exception or IRQ
  Trap --> Run: mret

Teaching cores implement a small CSR file and a single trap path — not the full privileged spec.

Wrong vs right

Wrong — treat CSR writes as combo into the same cycle’s mret.

Right — CSR write and trap entry are sequenced in the execute/WB stage; mepc captures the faulting (or next) PC per the spec you implement.