Wiki / Verification basics
Verification basics
Testbench structure, stimulus, and checking ideas for RTL.
Verification asks: does this RTL do what we meant? Start with a clear testbench, directed tests, and simple self-checks — then grow into constrained-random and assertions.
Pyramid (pragmatic)
Lint — catch careless RTL early Directed sim — hand-written scenarios Assertions — embed rules next to the design Coverage / CRV — later courses (SV / UVM)
Topics in this section
In RTL Studio
Use Learn labs with $dumpfile / $dumpvars, then open the VCD in Surfer. See also the simulation guide .
Simulate this in the Verilog IDE
Verification basics is easier to trust after a simulation than on a diagram alone. RTL Studio is a browser Verilog and SystemVerilog IDE: edit the RTL, lint with Slang, run the Verilator simulator, and read the VCD waveform in the same tab. Yosys synthesis is there when the code is structural RTL.
Open the Verilog IDE · Verilator simulation guide · Yosys synthesis guide
