If the sink registers ready (timing), it can go low one cycle late. A skid (or elastic) buffer stores the in-flight beat so the source still sees a clean handshake.
flowchart LR src[src] --> skid[skid_slot] skid --> dst[dst]
Typical implementation: a 2-deep registered FIFO, or an explicit “spill” flop plus mux.
Wrong vs right
Wrong — assign ready = ~busy when busy is a registered output of a long combo path (timing + lost beats).
Right — either combo ready with a short path, or a skid so registered ready is legal.